VLSI DOMAIN PROJECTS

S.NO

PROJECT TITILE

GTSV1

Low-Power and Area-Efficient Carry Select Adder

GTSV2

Design of Low-Power and High performance Radix-4 Multiplier

GTSV3

Design and Implementation of Automated Wave-Pipelined Circuit Using ASIC

GTSV4

A Novel Encoding Scheme for Low Power in Network on Chip Links

GTSV5

Synthesis and Array processor Realization of a 2-D IIR Beam Filter for Wireless Applications

GTSV6

HICPA: A Hybrid Low Power Adder for High-Performance Processors

GTSV7

Design and Implementation of a High Performance Multiplier using HDL

GTSV8

Design of Low Power TPG Using LP-LFSR

GTSV9

High Speed Signed Multiplier for Digital Signal Processing Applications

GTSV10

High speed Modified Booth Encoder multiplier for signed and unsigned numbers

GTSV11

Efficient Configurable Decoder Architecture for Non binary Quasi Cycle LDPC Codes

GTSV12

VLSI design and implementation of reconfigurable OFDM transceivers for software defined radio

GTSV13

Design & implementation of Memory-based cross-talk reducing algorithm to eliminate worst case crosstalk in on-chip VLSI interconnect.

GTSV14

Design and Implementation of Floating Point Multiplier

GTSV15

Design and Simulation of UART Serial Communication Module Based on VHDL

GTSV16

Design & Implementation of Area-optimized AES based on Verilog HDL

GTSV17

High Speed FPGA Design of Complex Multiplier Using Vedic Mathematics

GTSV18

A New Reversible Design of BCD Adder

GTSV19

FPGA based FFT Algorithm Implementation in WiMAX Communications System

GTSV20

Image Encryption Based On AES Key Expansion

GTSV21

Design of Serial Communication Interface based on FPGA

GTSV22

A Pipeline VLSI Architecture For HIGH-SPEED Computation Of the 1-D Discrete Wavelet Transforms

GTSV23

16- Bit RISC Processor design for convolution application

GTSV24

A Flexible Hardware Implementation of SHA-1 And SHA-2 Hash Functions

GTSV25

Design Of SHA-1 Algorithm based on FPGA

GTSV26

Design and implementation of fast unsigned 32-bit multiplier using VHDL

GTSV27

An Efficient Architecture Design for VGA Monitor Controller

GTSV28

Design and simulation of UART serial communication module based on VHDL

GTSV29

Direct Digital Synthesizer using non-uniform piecewise linear approximation

GTSV30

Design of low power and high speed configurable Booth Multiplier.

GTSV31

High Speed FPGA Design of Complex Multiplier Using Vedic Mathematics